1.1 Introducción histórica

• The current major family of Intel processors made its appearance in 1978 with the 8086 processor. (the 4004, 8080 and 8085 Intel processors were already in the market at that time)
• Along its evolution, since 1978, Intel has maintained upwards binary compatibility in the IA-32 processors. This compatibility ended with the Itanium and Itanium2 processors with the IA-64 architecture, totally incompatible with their predecessors
• The evolution of the Intel processors features is summarized in the next tables:
• The i386 was the first 32 bits processor from Intel. The operands and memory addressing are 32 bits wide, therefore, the i386 processor has a 4GB addressing space.
• The i386 is also the first processor to use paging, with a fixed 4KB page size. The previous processors used a segmentation scheme that can be obviated in the i386 using a flat memory model.
• The i386 was the first segmented processor, the i486 introduced the coprocessor inside the same chip and the Pentium, an APIC (Advanced Programable Interrupt Controller).

1.2 Basic execution environment

Execution Modes

Protected Mode

It is the normal working model of the processor, where all its features are available.

Real Addressing mode

It is a compatibility mode with the 8086, except for the instruction to switch to protected mode. The processor always boots up in this mode.

Management Mode

This is a mode entered through an APIC interruption, useful only for operating system management (power handling, security, etc.)

Basic Features

• The linear address space is of 4GB, although the physical memory can reach 64GB in some models.
• A normal program has 8 32-bit general purpose registers available, 6 16-bit segment registers, a 32-bit state register, EFLAGS, and a 32-bit instruction pointer EIP. These registers can be accessed from the general purpose operations: integer arithmetic instructions, flow control instructions, bit and byte-string operations and memory access instructions.
• A set of 8 80-bit floating point registers, a set of 8 64-bit and 128-bit MMX and XMM registers for SIMD operations.
• A set of resources for stack handling and subroutine invocation.
• The O.S. has also access to I/O ports, control registers for memory management, debugging, monitoring, etc.

1.2.1 General purpose registers

• The general purpose registers are the following:
  

  Although the general purpose registers can be used almost in any case, special care has to be taken with the stack pointer ESP.

• Additionally, these registers have special uses in some instructions:
  • EAX Accumulator register. Source and destination in some operations.
  • EBX Pointer to data in the DS segment.
  • ECX Counter in loop and and string operations.
  • EDX Pointer to the I/O ports.
  • ESI Source pointer in string operations and data pointer in the DS segment.
  • EDI Destination pointer in string operations and data pointer in the ES segment.
  • ESP Stack pointer.
  • EBP Pointer to data stored in the stack.

1.2.2 The EIP and EFLAG register

• The EIP register points to the next instruction to execute in the code segment. Its value is increased with the execution of each instruction or modified by the flow control instructions (JMP, Jxx, CALL, RET, RET n, IRET). This register is also commonly referred to as Program Counter
• The EFLAGS register contains the processor state, including the condition bits (S, Z, P, C, ...).
  
  • One of the most important bits from the O.S. viewpoint is the Interrupt Flag (IF). It controls if the processor must react to the maskable interrupt inputs. If it is set (1), the insterrupt requests are attended, otherwise they are ignored. It is not directly set or unset, but modified by the STI and CLI instructions.
  • Other important fields are the two bits of the IOPL indicator that denote the privilege level necessary to access the I/O ports, and the TF bit that indicates if the current process is being traced for debugging. In that case, instructions are executed step by step (producing an exception after each instruction).

1.3 The privilege levels

• IA-32 processors have 4 distinct privilege levels (0-3), being PL 0 the most privileged one.
  
• PL 0 is the privilege level that allows complete access to the processor resources. It is the level used by the O.S. since it needs to be able to execute any instruction and have access to all the I/O ports.
• PL 3 is the more restricted one. Applications usually run in that privilege level, where only general purpose instructions can be executed and no access to I/O ports is allowed. There are instructions available to grant access to I/O ports and the right to enable and disable interrupts. These instructions must be executed by the O.S. at PL 0 and remain in effect when the control is returned to the process at PL 3
• Linux uses only PL 0 and PL 3, which are denoted as kernel mode and user mode respectively.
• The current privilege level (CPL) can be found in bits 0 and 1 of the CS and SS registers.

1.4 Descriptor tables

• When the processor is in PL 0, the programmer has full access to a number of registers and data structures that control the behaviour of the processor, memory management, etc.
• The following figure shows a summary of these data structures and registers.
  
• The Global Descriptor Table (GDT) and the Local Descriptors Table (LDT) contain the information (descriptors ) related to the different segments that exist in the system. The segment registers (CS, DS, SS, ES, FS y GS) are indexes (selectors) to those tables.
  
• The Interrupt Descriptors Table (IDT) contains the interrupt vectors, along with information on access permissions, interrupts enabled, etc. In the interrupt descriptors there are selectors to the GDT or LDT tables.

1.5 Memory handling in protected mode

• The IA-32 architecture in protected mode has a memory model called segmentation+paging.
• To the logical addresses (the ones emitted by processes) go first through a segmentation scheme that gives as an output a linear address.
  
• Then, the linear address goes through the paging model, if it is active, to obtain the final physical address.
  
• The descriptor tables used in segmentation are accesed using the GDTR and LDTR registers, and are indexed with the segment registers or through the IDT entries:
  
• Although paging can be disabled in the IA-32 architecture, segmentation is always active.

1.5.1 Memory models

• In protected mode there are two possible memory models:
  • Flat model: All the segments have a base address 0 and 4GB limit. This is the model used in Linux since segmentation cannot be explicitly disabled.
    
  • Segmented model: Each memory area is contained in a segment, with specific properties and from where it is not possible to access the rest of memory.
    
• Besides the segments associated to a task, in the segmented model, the architecture provides a special kind of segment: the Task State Segment, where some properties of the task are stored. The IA-32 architecture defines a particular notion for "task", implemented in the processor hardware, that can or cannot be the task model used by the O.S.
  
  • The segment registers, the EIP registers, the EFLAGS , the base address of the page directory (CR3), the address of the LDT, pointers to the stacks of the different privilege levels, etc. are stored in this segment.
    

1.6 Interrupt and exception handling

• The IA-32 architecture uses a vectorized interrupt handling mechanism.
  • The interrupt controller sends an identifier of the received interrupt and this identifier is used as an index in the interrupt descriptors table (IDT) to decide the interrupt handling code to execute.
• The IDT holds an entry for each possible exception or interrupt. The base address of this table is in the IDTR register.
  
• Each entry contains a descriptor indicating what code has to be executed when the interrupt or exception occurs.
  

1.6.1 Invocation of an interrupt handler

• The invocation of an interrupt handler is illustrated in the following figure:
  
• When an interrupt handler is executed, the processor automatically stores the value of some registers in the stack of the current task. Thus, the processor can restore the state of the interrupted task once the interrupt handler returns (invoking IRET).
  
• The difference between calling a handler through a trap gate or an interrupt gate is that in the last case interrupts are automatically disabled.

1.7 Invocation of a function

• In C, the stack is the place where parameters are stored when invoking a function. Before making the call, the parameters are stored in the stack and then the function reads them from there.
• When the invocation to a function is done using instructions CALL and RET, the typical structure of the stack is like the one shown in the following figure:
  
• The insertion order in the stack is important. The last parameters to insert will be the first parameters in the function declaration.
• As we will see, the gcc compiler allows some directives intended to specify that a given function will receive the parameters in the general purpose registers.